Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing-Reference-Cited by-同舟云学术

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing

Published:2014 Issue:12 Volume:E97.A Page:2518-2529
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KONOURA Hiroaki¹²,ALNAJJAR Dawood¹²,MITSUYAMA Yukio²³,SHIMADA Hajime²⁴,KOBAYASHI Kazutoshi²⁵,KANBARA Hiroyuki²⁶,OCHI Hiroyuki²⁷,IMAGAWA Takashi⁸,WAKABAYASHI Kazutoshi⁹,HASHIMOTO Masanori¹²,ONOYE Takao¹²,ONODERA Hidetoshi²⁸

Affiliation:

1. Department of Information Systems Engineering, Osaka University

2. CREST, JST

3. School of Systems Engineering, Kochi University of Technology

4. Information Technology Center, Nagoya University

5. Graduate School of Science and Technology, Kyoto Institute of Technology

6. Advanced Scientific Technology & Management Research Institute of KYOTO

7. Graduate School of Information Science and Engineering, Ritsumeikan University

8. Department of Communications and Computer Engineering, Kyoto University

9. NEC Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E97.A/12/E97.A_2518/_pdf

Reference20 articles.

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2. [2] M.M. Azeem, S.J. Piestrak, O. Sentieys, and S. Pillement, “Error recovery technique for coarse-grained reconfigurable architectures,” Proc. DDECS, pp.441-446, April 2011.

3. [3] T. Schweizer, P. Schlicker, S. Eisenhardt, T. Kuhn, and W. Rosenstiel, “Low-cost TMR for fault-tolerance on coarse-grained reconfigurable architectures,” Proc. ReConFig, pp.135-140, Nov.-Dec. 2011.

4. [4] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, “Implementing flexible reliability in a coarse grained reconfigurable architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.21, no.12, pp.2165-2178, Dec. 2013.

5. [5] S.C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R.R. Taylor, “PipeRench: A reconfigurable architecture and compiler,” IEEE Trans. Comput., vol.33, no.4, pp.70-77, April 2000.

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