A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation-Reference-Cited by-同舟云学术

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation

Published:2013 Issue:1 Volume:E96.A Page:312-321
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KAWAMURA Kazushi¹,YANAGISAWA Masao²,TOGAWA Nozomu¹

Affiliation:

1. Department of Computer Science and Engineering, Waseda University

2. Department of Electronic and Photonic Systems, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/1/E96.A_312/_pdf

Reference13 articles.

1. [1] S. Abe, M. Yanagisawa, and N. Togawa, “An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures,” Proc. 2012 IEEE International Symposium on Circuits and Systems, pp.576-579, 2012.

2. [2] J. Cong, Y. Fan, X. Yang, and Z. Zhang, “Architecture and synthesis for multi-cycle communication,” Proc. 2003 International Symposium on Physical Design, pp.190-196, 2003.

3. [3] C. Constantinescu, “Impact of deep submicron technology on dependability of VLSI circuits,” Proc. Dependable Systems and Networks, pp.205-209, 2002.

4. [4] Z. Gu, Y. Yang, J. Wang, R.P. Dick, and L. Shang, “TAPHS: Thermal-aware unified physical-level and high-level synthesis,” Proc. 2006 Asia and South Pacific Design Automation Conference, pp.879-885, 2006.

5. [5] W. Huang, M.R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy, “Compact thermal modeling for temperature-aware design,” Proc. 41st annual Conference on Design Automation, pp.878-883, 2004.

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits;ITM Web of Conferences;2023