A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement-Reference-Cited by-同舟云学术

A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement

Published:2009 Issue:12 Volume:E92-A Page:3193-3202
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

CHEN Liang-Bi¹,YEH Chi-Tsai²,CHEN Hung-Yu¹,HUANG Ing-Jer¹

Affiliation:

1. Department of Computer Science and Engineering, National Sun Yat-Sen University

2. Department of Information Management, Shih-Chien University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E92.A/12/E92.A_12_3193/_pdf

Reference28 articles.

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4. [4] R.-T. Gu, T.-C. Yeh, W.-S. Huang, T.-Y. Huang, C.-H. Tsai, C.-N. Lee, M.-C. Chiang, S.-F. Hsiao, Y.-N. Chang, and I.-J. Huang, “A low cost tile-based 3D graphics full pipeline with real-time performance monitoring support for OpenGL ES in consumer electronics, ” Proc. 11th IEEE International Symposium on Consumer Electronics (ISCE'07), pp.1-6, July 2007.

5. [5] T.-Y. Ho, L.-B. Chen, and I.-J. Huang, “An efficient HW/SW integrated verification methodology for 3D graphics SoC development, ” Proc. 13th IEEE International Symposium on Consumer Electronics (ISCE'09), pp.927-931, May 2009.

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