An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits-Reference-Cited by-同舟云学术

An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits

Published:2009 Issue:12 Volume:E92-A Page:3136-3142
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

SHIOKI Kosuke¹,OKADA Narumi¹,ISHIHARA Toshiro¹,HIROSE Tetsuya¹,KUROKI Nobutaka¹,NUMA Masahiro¹

Affiliation:

1. Graduate School of Engineering, Kobe University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E92.A/12/E92.A_12_3136/_pdf

Reference8 articles.

1. [1] D. Brand, A. Drumm, S. Kundu, and P. Narain, “Incremental synthesis, ” Proc. ICCAD-94, pp.14-18, California, USA, Nov. 1994.

2. [2] H. Inoue, T. Iwasaki, T. Sugane, M. Numa, and K. Yamamoto, “Application of error diagnosis technique to incremental synthesis, ” IEICE Trans. Fundamentals, vol.E86-A, no.12, pp.3214-3217, Dec. 2003.

3. [3] M. Tomita, T. Yamamoto, F. Sumikawa, and K. Hirano, “Rectification of multiple logic design errors in multiple output circuits, ” Proc. 31st DAC, pp.212-217, California, USA, June 1994.

4. [4] M. Numa, H. Inoue, T. Kaimi, N. Kuroki, and K. Yamamoto, “An LUT-based multiple error diagnosis technique using symbolic simulation with truth variables, ” J. IPSJ, vol.43, no.5, pp.1252-1259, May 2002.

5. [5] T. Sugane, T. Iida, H. Inoue, N. Kuroki, M. Numa, and K. Yamamoto, “An LUT-based error diagnosis technique improved in multiplicity of rectifiable errors, ” Proc. MWSCAS2004, vol.I, pp.525-528, Hiroshima, Japan, July 2004.