Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC-Reference-Cited by-同舟云学术

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC

Published:2015 Issue:2 Volume:E98.A Page:476-484
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

XU Zule¹,LEE Seungjong¹,MIYAHARA Masaya¹,MATSUZAWA Akira¹

Affiliation:

1. Department of Physical Electronics, Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E98.A/2/E98.A_476/_pdf

Reference38 articles.

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4. [4] E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, “A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications,” IEEE J. Solid-State Circuits, vol.39, no.9, pp.1446-1454, Sept. 2004.

5. [5] M. Lee, M.E. Heidari, and A.A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE J. Solid-State Circuits, vol.44, no.10, pp.2808-2816, Oct. 2009.

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