A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs
Author:
Affiliation:
1. Graduate School of Information, Production and Systems, Waseda University
2. Faculty of Environmental Engineering, the University of Kitakyushu
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E99.A/12/E99.A_2412/_pdf
Reference20 articles.
1. [1] T.-Y. Lee, N.-Y. Lin, W.-C. Chen, and H. Wu, “An efficient task placement method for reconfigurable FPGA systems,” 2013 7th International Conference on Complex, Intelligent, and Software Intensive Systems, pp.451-455, 2013.
2. [2] C. Huriaux, O. Sentieys, and R. Tessier, “FPGA architecture support for heterogeneous, relocatable partial bitstreams,” 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-6, 2014.
3. [3] S. Hauck, “The future of reconfigurable systems,” 5-th Canadian Conference on Field Programmable Devices, Keynote Address, pp.1-7, 1998.
4. [4] T. Becker, W. Luk, and P.Y.K. Cheung, “Enhancing relocatability of partial bitstreams for run-time reconfiguration,” 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), pp.35-44, 2007.
5. [5] Xilinx Partial Reconfigurable User Guide, UG909, 2016.
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