1. [1] N.K. Jha and S. Gupta, Testing of Digital Systems, Cambridge University Press, 2012. 10.1017/cbo9780511816321
2. [2] L.T. Wang, C.W. Wu, and X. Wen, eds., VLSI Test Principles and Architectures — Design for Testability, The Morgan Kaufmann Series in Systems on Silicon, Morgan Kaufmann Publishers, 2006.
3. [3] Y. Higami, S. Wang, H. Takahashi, and K.K. Saluja, “Adaptive field diagnosis for reducing the number of test patterns,” Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp.412-415, July 2017.
4. [4] C. Xue and R. Blanton, “Test-set reordering for improving diagnosability,” Proc. 2017 IEEE 35th VLSI Test Symposium (VTS), pp.1-6, 2017. 10.1109/vts.2017.7928926
5. [5] K.Y. Cho and E.J. McCluskey, “Test set reordering using the gate exhaustive test metric,” Proc. 25th IEEE VLSI Test Symposium (VTS'07), pp.199-204, 2007. 10.1109/vts.2007.79