An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement
Author:
Affiliation:
1. IBM Quantum, IBM Research - Tokyo
2. Graduate School of Information Science and Engineering, Ritsumeikan University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E106.A/2/E106.A_2022EAP1050/_pdf
Reference23 articles.
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2. [2] P.W. Shor, “Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer,” SIAM J. Comput., vol.26, no.5, pp.1484-1509, Oct. 1997. 10.1137/s0097539795293172
3. [3] S. Yamashita, S. Minato, and M.D. Michael, “DDMF: An efficient decision diagram structure for design verification of quantum circuits under a practical restriction,” IEICE Trans. Fundamentals, vol.E91-A, no.12, pp.3793-3802, Dec. 2008. 10.1093/ietfec/e91-a.12.3793
4. [4] A. Barenco, C.H. Bennett, R. Cleve, D.P. DiVincenzo, N. Margolus, P. Shor, T. Sleator, J. Smolin, and H. Weinfurter, “Elementary gates for quantum computation,” 1995. cite arxiv:quant-ph/9503016Comment: 31 pages, plain latex, no separate figures, submitted to Phys. Rev. A. Related information on http://vesta.physics.ucla.edu:7777/ 10.48550/arXiv.quant-ph/9503016
5. [5] D.M. Miller, R. Wille, and Z. Sasanian, “Elementary quantum gate realizations for multiple-control toffoli gates,” 2011 41st IEEE International Symposium on Multiple-Valued Logic, pp.288-293, May 2011. 10.1109/ismvl.2011.54
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