Affiliation:
1. Okayama Prefectural University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Reference9 articles.
1. [1] B. Landgraf, “MOM capacitance measurements in a 130nm CMOS node,” 2015 Austrian Workshop on Microelectronics, pp.42-45, 2015. 10.1109/austrochip.2015.10
2. [2] H. Omran, H. Alahmadi, and K.N. Salama, “Matching properties of femtofarad and sub-femtofarad MOM capacitors,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.63, no.6, pp.763-772, June 2016. 10.1109/tcsi.2016.2537824
3. [3] T. Sakurai and K. Tamaru, “Simple formulas for two- and three-dimensional capacitances,” IEEE Trans. Electron Devices, vol.ED-30, no.2, pp.183-185, Feb. 1983. 10.1109/t-ed.1983.21093
4. [4] S.-C. Wong, G.-Y. Lee, and D.-J. Ma, “Modeling of interconnect capacitance, delay, and crosstalk in VLSI,” IEEE Trans. Semicond. Manuf., vol.13, no.1, pp.108-111, Feb. 2000. 10.1109/66.827350
5. [5] N. Itoh, T. Ohguro, K. Katoh, H. Kimijima, S. Ishizuka, K. Kojima, and H. Miyakawa, “Scalable parasitic components model of CMOS for RF circuit design,” IEICE Trans. Fundamentals, vol.E86-A, no.2, pp.288-298, Feb. 2003.
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