High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA-Reference-Cited by-同舟云学术

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High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA

Published:2019-12-01 Issue:12 Volume:E102.A Page:1792-1803
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

RANAWAKA Piyumal¹,EKPANYAPONG Mongkol²,TAVARES Adriano³,DAILEY Mathew⁴,ATHIKULWONGSE Krit⁵,SILVA Vitor³

Affiliation:

1. University of Moratuwa

2. Micro-electronics and Embedded Systems, Asian Institute of Technology

3. Department of Industrial Electronics, University of Minho

4. The Department of Information and Communication Technologies, Asian Institute of Technology

5. National Electronics and Computer Technology Centre, National Science and Technology Development Agency

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E102.A/12/E102.A_1792/_pdf

Reference17 articles.

1. [1] N. Dalal and B. Triggs, “Histogram of gradients for human detection,” Proc. 2005 International Conference on Computer Vision and Pattern Recognition, vol.2, pp.886-893, IEEE Computer Society, Washington, DC, USA, 2005. 10.1109/cvpr.2005.177

2. [2] L. Zang and R. Nevatia, “Efficient scan-window based object detection using GPGPU,” IEEE, CVPRW, 2008. 10.1109/cvprw.2008.4563097

3. [3] S. Baur, U. Brusmann, and S. Schlotterbeck-Macht, “FPGA implementation of a HOG-based pedestrian recognition system,” MPC-Workshop, July 2009.

4. [4] M. Hiromoto and R. Miyamoto, “Hardware architecture for high accuracy real-time pedestrian detection with CoHOG features,” IEEE ICCVW, 2009. 10.1109/iccvw.2009.5457609

5. [5] R. Kadota, H. Sugano, M. Hiromoto, H. Ochi, R. Miyamoto, and Y. Nakamura, “Hardware architecture for HOG feature extraction,” Proc.2009 International Conference on Intelligent Information Hiding and Multimedia Signal Processing, pp.1330-1333, IEEE Computer Society, Washington DC, USA, 2009. 10.1109/iih-msp.2009.216

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