A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution

Author:

SATO Shimpei1,SASSA Eijiro1,UKON Yuta1,TAKAHASHI Atsushi1

Affiliation:

1. Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference17 articles.

1. [1] K. Ando and A. Takahashi, “Performance evaluation of various configuration of adder in variable latency circuits with error detection/correction mechanism,” SASIMI 2012 Proceedings, pp.549-554, 2012.

2. [2] S. Sato, H. Nakatsuka, and A. Takahashi, “Performance improvement of general-synchronous circuits by variable latency technique using dynamic timing-error detection,” SASIMI 2016 Proceedings, pp.1-4, 2016.

3. [3] S. Sato, E. Sassa, Y. Ukon, and A. Takahashi, “A low area overhead design for high-performance general-synchronous circuits with speculative execution,” Proc. 2019 IEEE International Symposium on Circuits and Systems (ISCAS 2019), pp.1-5, 2019. 10.1109/iscas.2019.8702333

4. [4] J.P. Fishburn, “Clock skew optimization,” IEEE Trans. Comput., vol.39, no.7, pp.945-951, July 1990. 10.1109/12.55696

5. [5] E. Friedman, “Clock distribution networks in synchronous digital integrated circuits,” Proc. IEEE, vol.89, no.5, pp.665-692, 2001. 10.1109/5.929649

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