Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density-Reference-Cited by-同舟云学术

Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density

Published:2010 Issue:12 Volume:E93-A Page:2372-2379
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

CHEN Song¹,SHEN Jianwei¹,GUO Wei¹,CHIANG Mei-Fang¹,YOSHIMURA Takeshi¹

Affiliation:

1. Graduate School of IPS, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E93.A/12/E93.A_12_2372/_pdf

Reference16 articles.

1. Full-Chip Routing Considering Double-Via Insertion

2. [2] T. Huang, C. Yao, W. Wan, C. Hsia, and M. Liang, “Numerical modeling and characterization of the stress migration behaviour upon various 90 nanometer cu/low k interconnects,” Proc. IEEE 2003 International, Interconnect Technology Conference, pp.207-209, June 2003.

3. [3] N. Harrison, “A simple via duplication tool for yield enhancement,” Proc. 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.39-47, 2001.

4. [4] J.G. Xi, “Improving yield in rtl-to-gdsii flows,” EE Times, July 2005.

5. [5] G. Xu, L.D. Huang, D. Pan, and M. Wong, “Redundant-via enhanced maze routing for yield improvement,” Asia and South Pacific Conference on Design Automation, Proc. ASP-DAC 2005, vol.2, pp.1148-1151, Jan. 2005.

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-08

2. A rule conflict resolution method based on Vague set;Soft Computing;2013-07-02