1.5-GHz Spread-Spectrum PHY Using Reference Clock with 400-ppm Frequency Tolerance for SATA Application-Reference-Cited by-同舟云学术

1.5-GHz Spread-Spectrum PHY Using Reference Clock with 400-ppm Frequency Tolerance for SATA Application

Published:2015 Issue:2 Volume:E98.A Page:485-491
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KAWAMOTO Takashi¹,SUZUKI Masato²,NOTO Takayuki²

Affiliation:

1. Hitachi Central Research Laboratory

2. Renesas Electronics Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E98.A/2/E98.A_485/_pdf

Reference9 articles.

1. [1] Serial ATA International Organization, “SATA: High speed serialized AT attachment,” Rev. 2.6, Oct. 2006.

2. [2] M. Aoyama, K. Ogasawara, M. Sugawara, T. Ishibashi, S. Shimoyama, K. Yamagushi, T. Tanagita, and T. Noma, “3Gbps, 5000ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for serial ATA,” Dig. Symp. VLSI Circuits, pp.107-110, June 2003.

3. [3] H.R. Lee, O. Kim, G. Ahn, and D.K. Jeong, “A low-jitter 5000ppm spread-spectrum clock generator for multi-channel STAT transceiver in 0.18µm CMOS,” IEEE ISSCC, Digest of Tech. Papers, pp.162-163, Feb. 2005.

4. [4] J.-S. Pan, T.-H. Hsu, H.-C. Chen, J.-W. Chen, B.-Y. Hsieh, H.-C. Chen, W.-H. Tu, C.-M. Chang, R. Lee, C.-H. Chu, Y.-C. Liu, C.-C. Hsiao, C. Lui, L. Huang, C.-H. Chou, C.-L. Wu, M.-H. Liu, S.-P. Chen, B. Liu, H.-S. Hsu, C.-Y. Lin, S.-N. Tsai, J.-N. Yang, S. Chien, K.-H. Chao, C.-P. Ma, C. Yung, S.-H. Chou, Y.-S. Weng, M.-S. Tsai, K.-H. Hsieh, K.-J. Chang, J.-C. Hsu, H.-C. Peng, and A. Ho, “Fully integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications with n-chip 4-LVDS channel WSG and 1.5Gb/s SATA PHY,” IEEE ISSCC, Digest of Tech. Paper, pp.266-267, Feb. 2006.

5. [5] M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-spectrum clock generator for serial ATA using fractional SSCG controlled by ΣΔ modulator with level shifter,” IEEE ISSCC, Digest of Tech. Papers, pp.160-160, Feb. 2005.