Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit

Author:

SUGAWARA Hirotaka1,OKADA Kenichi1,MASU Kazuya1

Affiliation:

1. Integrated Research Institute, Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference32 articles.

1. [1] H. Tsurumi and Y. Suzuki, “Broadband RF architecture for software-defined radio in handheld terminal applications, ” IEEE Commun. Mag., vol.31, no.2, pp.90-95, Feb. 1999.

2. [3] K. Okada, Y. Yoshihara, H. Sugawara, and K. Masu, “Dynamic reconfigurable RF circuit architecture, ” Asia South Pacific Design Automation Conf., pp.683-686, Shanghai, China, Jan. 2005.

3. [4] L. Perraud, C. Pinatel, M. Recouly, J.L. Bonnot, N. Sornin, F. Benoist, M. Massei, and O. Gibrat, “A dual-band 802.11a/b/g radio in 0.18µm CMOS, ” IEEE ISSCC Dig. Tech. Papers, pp.94-95, San Francisco, California, Feb. 2004.

4. [5] M. Zargari, S. Jen, B. Kaczynski, M. Lee, M. Mack, S. Mehta, S. Mendis, K. Onodera, H. Samavati, W. Si, K. Singh, A. Tabatabaei, M. Terrovitis, D. Weber, D. Su, and B. Wooley, “A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g WLAN, ” IEEE ISSCC Dig. Tech. Papers, pp.95-96, San Francisco, California, Feb. 2004.

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1. RF Front-End and Complex BPF for Reconfigurable Low-IF Receiver;IEICE Transactions on Electronics;2013

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