Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation

Author:

HIRAKAWA Natsumi1,FUJIYOSHI Kunihiro1

Affiliation:

1. Department of Electrical and Electronic Engineering, Tokyo University of Agriculture and Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Reference15 articles.

1. [1] R. Okuda, T. Sato, H. Onodera, and K. Tamaru, “An algorithm for layout compaction problem with symmetry constraints, ” IEICE Trans. Fundamentals (Japanese Edition), vol.J73-A, no.3, pp.536-543, March 1990.

2. [2] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “Rectangle-packing-based module placement, ” Proc. IEEE ICCAD, pp.472-479, 1995.

3. [3] T. Takahashi, “A new encoding scheme for rectangle packing problem, ” Proc. ASPDAC, pp.175-178, 2000.

4. [4] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, “B*-trees: A new representation for non-slicing floorplans, ” Proc. DAC, pp.458-463, 2000.

5. [5] Y.-X. Pang, F. Balasa, K. Lampaert, and C.-K. Cheng, “Block placement with symmetry constraints based on the O-tree non-slicing representation, ” Proc. DAC, pp.464-467, 2000.

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