Affiliation:
1. Graduate School of Information, Production and Systems, Waseda University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Reference22 articles.
1. [1] Z. Huang, A. Kurokawa, Y. Yang, H. Yu, and Y. Inoue, “Modeling the influence of input-to-output coupling capacitance on CMOS inverter delay,” IEICE Trans. Fundamentals, vol.E89-A, no.4, pp.840-846, April 2007.
2. [2] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, “Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.29, no.2, pp.250-260, Feb. 2010.
3. [3] L. Ding, Z. Huang, M. Jiang, A. Kurokawa, and Y. Inoue, “Modeling the overshooting effect of multi-input gate in nanometer technologies,” MWSCAS2011, pp.1-4, Seoul, Aug. 2011.
4. [4] L. Bisdounis, “Analytical modeling of overshooting effect in sub-100nm CMOS inverters,” J. Circuits, Systems, and Computers, vol.20, no.7, pp.1303-1321, Nov. 2011.
5. [5] L.M. Brocco, S.P. McCormick, and J. Allen, “Macromodeling CMOS circuits for timing simulation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.7, no.12, pp.1237-1249, Dec. 1988.