A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits
Author:
Affiliation:
1. Graduate School of Informatics, Kyoto University
2. Graduate School of Informatics, Nagoya University
3. NTT Nanophotonics Center
4. NTT Basic Research Laboratories
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E104.A/11/E104.A_2020KEP0018/_pdf
Reference18 articles.
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2. [2] A. Ceyhan, M. Jung, S. Panth, S.K. Lim, and A. Naeemi, “Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts,” Proc. IEEE Interconnect Technology Conference/Advanced Metallization Conference, pp.345-348, May 2014. 10.1109/iitc.2014.6831831
3. [3] W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45nm early design exploration,” IEEE Trans. Electron Devices, vol.53, no.11, pp.2816-2823, Nov. 2006. 10.1109/ted.2006.884077
4. [4] Y. Vlasov, “Silicon photonics for next generation computing systems,” Proc. European Conference on Optical Communications, pp.1-2, Sept. 2008. 10.1109/ecoc.2008.4729553
5. [5] N. Yamamoto, T. Ogawa, and K. Komori, “Photonic crystal directional coupler switch with small switching length and wide bandwidth,” Opt. Express, vol.14, no.3, pp.1223-1229, Feb. 2006. 10.1364/oe.14.001223
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