Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation-Reference-Cited by-同舟云学术

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Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation

Published:2021-11-01 Issue:11 Volume:E104.A Page:1477-1487
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

HATTORI Naoki¹,SHIOMI Jun²,MASUDA Yutaka¹,ISHIHARA Tohru¹,SHINYA Akihiko³,NOTOMI Masaya⁴

Affiliation:

1. Nagoya University

2. Kyoto University

3. NTT Nanophotonics Center

4. NTT Basic Research Laboratories

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E104.A/11/E104.A_2020KEP0016/_pdf

Reference24 articles.

1. [1] T. Ishihara, J. Shiomi, N. Hattori, Y. Masuda, A. Shinya, and M. Notomi, “An optical neural network architecture based on highly parallelized WDM-multiplier-accumulator,” Proc. IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, Information and Computing Systems, pp.15-21, Nov. 2019. 10.1109/photonics49561.2019.00008

2. [2] A. Ceyhan, M. Jung, S. Panth, S.K. Lim, and A. Naeemi, “Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts,” Proc. IEEE Interconnect Technology Conference/Advanced Metallization Conference, pp.345-348, May 2014. 10.1109/iitc.2014.6831831

3. [3] Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, New York, NY, 2011. 10.1007/978-1-4614-0445-3

4. [4] S. Sinha, B. Cline, G. Yeric, V. Chandra, and Y. Cao, “Design benchmarking to 7nm with FinFET predictive technology models,” Proc. International Symposium on Low Power Electronics and Design, pp.15-20, July 2012. 10.1145/2333660.2333666

5. [5] X. Wu, J. Xu, Y. Ye, Z. Wang, M. Nikdast, and X. Wang, “SUOR: Sectioned undirectional optical ring for chip multiprocessor,” J. Emerg. Technol. Comput. Syst., vol.10, no.4, pp.1-25, April 2014. 10.1145/2600072

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