A Novel Procedure for Implementing a Turbo Decoder on a GPU with Coalesced Memory Access-Reference-Cited by-同舟云学术

A Novel Procedure for Implementing a Turbo Decoder on a GPU with Coalesced Memory Access

Published:2017 Issue:5 Volume:E100.A Page:1188-1196
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

AHN Heungseop¹,CHOI Seungwon¹

Affiliation:

1. Dept. of Electronic and Computer Engineering, Hanyang University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E100.A/5/E100.A_1188/_pdf

Reference28 articles.

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2. [2] H. Holma and A. Toskala, WCDMA for UMTS: Radio Access for Third Generation Mobile Communications, John Wiley & Sons, West Sussex, England, 2002.

3. [3] E. Dahlman, S. Parkvall, and J. Skold, 4G LTE/LTE-Advanced for Mobile Broadband, Academic Press, 2011.

4. [4] C. Studer, C. Benkeser, S. Belfanti, and Q. Huang, “Design and implementation of a parallel turbo-decoder ASIC for 3GPP-LTE,” IEEE J. Solid-State Circuits, vol.46, no.1, pp.8-17, Jan. 2011.

5. [5] Xilinx Corporation, LogiCORE IP 3GPP Mixed Mode Turbo Decoder v2.0, Xilinx Corporation, 2015. http://www.xilinx.com/support/documentation/ip_documentation/tcc_decoder_3gppmm/v2_0/pb009_tcc_decoder_3gppmm.pdf

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