Accurate Nanopower Supply-Insensitive CMOS Unit <i>V<sub>th</sub></i> Extractor and <i>αV<sub>th</sub></i> Extractor with Continuous Variety-Reference-Cited by-同舟云学术

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Accurate Nanopower Supply-Insensitive CMOS Unit V_th Extractor and αV_th Extractor with Continuous Variety

Published:2017 Issue:5 Volume:E100.A Page:1145-1155
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

WANG Jing¹,DING Li¹,LI Qiang¹,SHINOHARA Hirofumi¹,INOUE Yasuaki¹

Affiliation:

1. Graduate School of Information, Production and Systems, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E100.A/5/E100.A_1145/_pdf

Reference21 articles.

1. [1] H.G. Lee, S.Y. Oh, and G. Fuller, “A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET,” IEEE Trans. Electron Devices, vol.29, no.2, pp.346-348, Feb. 1982.

2. [2] Z. Wang, “A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance,” IEEE J. Solid-State Circuits, vol.26, no.9, pp.1293-1301, Sep. 1991.

3. [3] Z. Wang, “Automatic VT extractors based on an n x n2 MOS transistors array and their application,” IEEE J. Solid-State Circuits, vol.27, no.9, pp.1277-1285, Sept. 1992.

4. [4] M.G. Johnson, “An input-free VT extractor circuit using a two-transistor differential amplifier,” IEEE J. Solid-State Circuits, vol.28, no.6, pp.704-705, June 1993.

5. [5] C.G. Yu and R.L. Geiger, “An accurate and matching-free threshold voltage extraction scheme for MOS transistors,” Proc. IEEE Int. Symp. on Circuits and Systems, vol.4, pp.115-118, London, May 1994.

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