Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme-Reference-Cited by-同舟云学术

Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme

Published:2017 Issue:7 Volume:E100.A Page:1363-1373
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

SAITO Hiroshi¹,IMAI Masashi²,YONEDA Tomohiro³

Affiliation:

1. University of Aizu

2. Hirosaki University

3. National Institute of Informatics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E100.A/7/E100.A_1363/_pdf

Reference12 articles.

1. [1] P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvisi, “Modeling the effect of technology trends of the soft error rate of combinational logics,” Proc. DSN, pp.389-398, 2002. 10.1109/dsn.2002.1028924

2. [2] S. Pae, J. Maiz, C. Prasad, and B. Woolery, “Effect of BTI degradation on transistor variability in advanced semiconductor technologies,” IEEE Trans. Device Mater. Rel., vol.8, no.3, pp.519-525, 2008. 10.1109/tdmr.2008.2002351

3. [3] T. Yoneda, M. Imai, H. Saito, and K. Kise, “Dependable real-time task execution scheme for a many-core platform,” Proc. DFTS, pp.198-205, 2015. 10.1109/dft.2015.7315162

4. [4] K. Sato et al., “A study on performance evaluation of highly reliable multiple-core systems with DTTR method,” IPSJ SIG Technical Report, vol.2015-SLDM-172, no.11, pp.57-62, Oct., 2015 (in Japanese).

5. [5] H. Saito, M. Imai, and T. Yoneda, “A task allocation method for the DTTR scheme based on task scheduling of fault patterns,” Proc. ISCAS, pp.22-25, 2016. 10.1109/iscas.2016.7527214