A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning-Reference-Cited by-同舟云学术

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A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning

Published:2017 Issue:7 Volume:E100.A Page:1473-1480
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

IHARA Takeshi¹,HONGO Toshiyuki¹,TAKAHASHI Atsushi¹,KODAMA Chikaaki²

Affiliation:

1. Tokyo Institute of Technology

2. Toshiba Corporation

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E100.A/7/E100.A_1473/_pdf

Reference19 articles.

1. [1] T. Ihara, T. Hongo, A. Takahashi, and C. Kodama, “Grid-based self-aligned quadruple patterning aware two dimensional routing pattern,” Proc. Design, Automation and Test in Europe (DATE 2016), pp.241-244, 2016. 10.3850/9783981537079_0544

2. [2] B. Yu, K. Yuan, B. Zhang, D. Ding, and D.Z. Pan, “Layout decomposition for triple patterning lithography,” Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.1-8, 2011. 10.1109/iccad.2011.6105297

3. [3] B. Yu, Y.H. Lin, G. Luk-Pat, D. Ding, K. Lucas, and D.Z. Pan, “A high-performance triple patterning layout decomposer with balanced density,” Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.163-169, 2013. 10.1109/iccad.2013.6691114

4. [4] T. Matsui, Y. Kohira, C. Kodama, and A. Takahashi, “Positive semidefinite relaxation and approximation algorithm for triple patterning lithography,” Proc. 25th International Symposium on Algorithms and Computation (ISAAC), LNCS 8889, pp.365-375, 2014. 10.1007/978-3-319-13075-0_29

5. [5] B. Yu, J.R. Gao, and D.Z. Pan, “Triple patterning lithography (TPL) layout decomposition using end-cutting,” Proc. SPIE, Design for Manufacturability through Design-Process Integration VII, 8684, 86840G, 2013. 10.1117/12.2011355

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