A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication-Reference-Cited by-同舟云学术

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication

Published:2010 Issue:7 Volume:E93-A Page:1300-1308
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

CHEN Chia-I¹,HUANG Juinn-Dar¹

Affiliation:

1. Department of Electronics Engineering and the Institute of Electronics, National Chiao Tung University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E93.A/7/E93.A_7_1300/_pdf

Reference33 articles.

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4. [4] W.J. Dally, “Interconnect-limited VLSI architecture, ” IEEE Int'l Conf. Interconnect Technology, 1999.

5. [5] Y. Mori, V. Moshnyaga, H. Onodera, and K. Tamaru, “A performance-driven macro-block placer for architectural evaluation of ASIC designs, ” Proc. Annual IEEE Int'l ASIC Conf. and Exhibit, pp.233-236, Sept. 1995.

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