SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines-Reference-Cited by-同舟云学术

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

Published:2013 Issue:12 Volume:E96.A Page:2561-2567
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

YAMASHITA Jun¹,YOTSUYANAGI Hiroyuki¹,HASHIZUME Masaki¹,KINOSHITA Kozo²

Affiliation:

1. Institute of Technology and Science, The University of Tokushima

2. Osaka Gakuin University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/12/E96.A_2561/_pdf

Reference18 articles.

1. [1] H. Takahashi, Y. Higami, T. Kikkawa, T. Aikyo, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi, and M. Hashizume, “Test generation and diagnostic test generation for open faults with considering adjacent lines,” Proc. International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp.243-251, 2007.

2. [2] S.M. Reddy, I. Pomeranz, and C. Liu, “On tests to detect via opens in digital CMOS circuits,” Proc. 45th ACM/IEEE Design Automation Conference, pp.840-845, 2008.

3. [3] R. Gomez, A. Giron, and V.H. Champac, “A test generation methodology for interconnection opens considering signals at the coupled lines,” Journal of Electronic Testing: Theory and Applications, vol.24, no.6, pp.529-538, Dec. 2008.

4. [4] R. Kuribayashi, H. Yotsuyanagi, and M. Hashizume, “Test generation for open faults considering the effects of adjacent lines,” 10th IEEE Workshop on RTL and High Level Testing (WRTLT09), pp.61-66, 2009.

5. [5] D. Arumi, R. Rodriguez-Montanes, J. Figueras, S. Eichenberger, C. Hora, and B. Kruseman, “Diagnosis of interconnect full open defects in the presence of fan-out,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.30, no.12, pp.1911-1922, Dec 2011.