A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation-Reference-Cited by-同舟云学术

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation

Published:2013 Issue:12 Volume:E96.A Page:2533-2541
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

FUJIMOTO Daisuke¹,KATASHITA Toshihiro²,SASAKI Akihiko²,HORI Yohei²,SATOH Akashi³,NAGATA Makoto¹

Affiliation:

1. Graduate School of System Informatics, Kobe University

2. National Institute of Advanced Industrial Science and Technology

3. Graduate School of Infomatics and Engineering, The University of Electro-Communications

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/12/E96.A_2533/_pdf

Reference15 articles.

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2. [2] E. Brier, C. Clavier, and F. Olivier, “Correlation power analysis with a leakage model,” Proc. 2004 Intl. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2004), LNCS 3156, pp.16-29, 2004.

3. [3] S. Mangard, E. Oswald, and T. Popp, Power Analysis Attacks, Springer Science Business Media, LLC, 2007.

4. [4] D. Hwang, K. Tiri, A. Hodjat, B-C. Lai, S. Yang, P. Schaumount, and I. Verbauwhede, “AES-based security coprocessor IC in 0.18-µm CMOS with resistance to differential power analysis side-channel attacks,” IEEE J. Solid-State Circuits, vol.41, no.4, pp.781-792, April 2006.

5. [5] K. Tiri and I. Verbauwhede, “A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation,” Proc. Design, Automation and Test in Europe Conference (DATE 2004), pp.246-251, 2004.

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