A glitch energy reduction method with low complexity dynamic element matching for data converters
Author:
Affiliation:
1. School of Microelectronics, Xidian University
2. Radiation Resistant Integrated Circuit Technology Laboratory of China Aerospace Science and Technology Group Corporation
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/20/5/20_20.20220529/_pdf
Reference31 articles.
1. [1] S. Jang, et al.: “Temperature sensor circuit with dynamic element matching in CMOS 65nm for a mmWave beamformer,” 2021 International Conference on Information and Communication Technology Convergence (ICTC) (2021) 1390 (DOI: 10.1109/ICTC52510.2021.9621051).
2. [2] M. Kilic, et al.: “A row-column accessed dynamic element matching DAC architecture for SAR ADCs,” IEEE Nordic Circuits and Systems Conference (2018) 1 (DOI: 10.1109/NORCHIP.2018.8573513).
3. [3] L. Lai, et al.: “Demystifying and mitigating code-dependent switching distortions in current-steering DACs,” IEEE Trans. Circuits Syst. I, Reg. Papers 66 (2019) 68 (DOI: 10.1109/TCSI.2018.2866819).
4. [4] M. Shen, et al.: “Random swapping dynamic element matching technique for glitch energy minimization in current-steering DAC,” IEEE Trans. Circuits Syst. II, Exp. Briefs 57 (2010) 369 (DOI: 10.1109/TCSII.2010.2043400).
5. [5] K. Obata, et al.: “A 97.99dB SNDR, 2kHz BW, 37.1μW noise-shaping SAR ADC with dynamic element matching and modulation dither effect,” 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) (2016) 1 (DOI: 10.1109/VLSIC.2016.7573463).
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