A method of defense against cache timing attack in non-volatile memory-Reference-Cited by-同舟云学术

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A method of defense against cache timing attack in non-volatile memory

Published:2023-03-25 Issue:6 Volume:20 Page:20220477-20220477
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Choi Juhee¹

Affiliation:

1. Dept. of Smart Information Communication Engineering, Sangmyung University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/20/6/20_20.20220477/_pdf

Reference31 articles.

1. [1] F. Liu, et al.: “Last-level cache side-channel attacks are practical,” IEEE Symposium on Security and Privacy (2015) 605 (DOI: 10.1109/SP.2015.43).

2. [2] Z. He and R.B. Lee: “How secure is your cache against side-channel attacks?,” Annual IEEE/ACM International Symposium on Microarchitecture (2017) 341 (DOI: 10.1145/3123939.3124546).

3. [3] M. Lipp, et al.: “Meltdown: reading kernel memory from user space,” Communications of the ACM 63 (2020) 46 (DOI: 10.1145/3357033).

4. [4] P. Kocher, et al.: “Spectre attacks: exploiting speculative execution,” Communications of the ACM 63 (2020) 93 (DOI: 10.1145/3399742).

5. [5] A. Prout, et al.: “Measuring the impact of spectre and meltdown,” IEEE High Performance Extreme Computing Conference (2018) 1 (DOI: 10.1109/HPEC.2018.8547554s).

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