DC-Balanced Improvement of Interlaken Protocol

Author:

YOOWATTANA Sarat1,EKPANYAPONG Mongkol1

Affiliation:

1. Asian Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Software

Reference24 articles.

1. [1] A. Athavale and C. Christensen, “High-speed serial io made simple, a designers' guide, with FPGA applications,” Connectivity Solution, Edition 1.0, Xilinx.

2. [2] J.D.H. Alexander, “Clock recovery from random binary signals,” Electron. Lett., vol.11, no.22, pp.541-542, 1975. doi: 10.1049/el:19750415 10.1049/el:19750415

3. [3] J. Saade, A. Goulahsen, A. Picco, J. Huloux, and F. Petrot, “Low overhead, DC-balanced and run length limited line coding,” Signal and Power Integrity (SPI), 2015 IEEE 19th Workshop on, pp.1-4, May 2015. 10.1109/sapiw.2015.7237405

4. [4] BOSCH, CAN specification.

5. [5] W.M. Barrett, “Disparity reduction for high speed serial links,” US Patent US 9,007,240 B2, April 2015.

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