1. [1] B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits and Syst. II: Analog and Digital Signal Process., vol.44, no.6, pp.428-435, June 1997.
2. [2] J. Crols and M.S.J. Steyaert, “A single-chip 900MHz CMOS receiver front-end with a high performance low-IF topology,” IEEE J. Solid-State Circuits, vol.30, no.12, pp.1483-1492, Dec. 1995.
3. [3] H. Tsurumi, H. Yoshida, S. Otaka, H. Tanimoto, and Y. Suzuki, “Broadband and flexible receiver architecture for software defined radio terminal using direct conversion and low-IF principle,” IEICE Trans. Commun., vol.E83-B, no.6, pp.1246-1253, June 2000.
4. [4] Y. Sanada and M. Ikehara, “Digital compensation scheme for coefficient errors of a complex filter bank parallel A/D converter in low-IF receivers,” IEICE Trans. Commun., vol.E85-B, no.12, pp.2656-2662, Dec. 2002.
5. [5] C. Muto and H. Hoshikawa, “An integrable image rejection system using a complex analog filter with variable bandwidth and center frequency characteristics,” IEICE Trans. Fundamentals, vol.E85-A, no.2, pp.309-315, Feb. 2002.