Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches
Author:
Affiliation:
1. College of Computer, National University of Defense Technology
2. Graduate School of Science and Engineering, Ibaraki University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Software
Link
https://www.jstage.jst.go.jp/article/transcom/E102.B/9/E102.B_2018EBP3333/_pdf
Reference38 articles.
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