A Novel 400-Gb/s (100-Gb/s × 4) Physical-Layer Architecture Using Low-Power Technology

Author:

KONO Masashi1,KANBE Akihiro1,TOYODA Hidehiro1,NISHIMURA Shinji1

Affiliation:

1. Hitachi, Ltd., Central Research Laboratory

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Software

Reference18 articles.

1. [1] IEEE Std 802.3ba-2010, “Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD Access Method),” IEEE, 2010.

2. [4] H. Toyoda, M. Okuno, S. Nishimura, and M. Terada, “A 100Gb/s and high-reliable physical-layer architecture for VSR and backplane Ethernet,” ICC 2008 in Beijing, China (IEEE International Conference on Communications), ON2-1, May 2008.

3. [5] M. Kono, H. Toyoda, and A. Kanbe, “High-speed and low-power control technologies for next generation Ethernet,” IEICE Technical Report, OCS2010-20, June 2010.

4. [6] M. Kono, A. Kanbe, and H. Toyoda, “A 400-Gb/s and low-power physical-layer architecture for next-generation Ethernet,” ICC2011 Kyoto, Japan (IEEE International Conference on Communications), ONS-P, June 2011.

5. [7] P.S. Henry, “Lightwave primer,” IEEE J. Quantum Electron., vol.QE-21, no.12, pp.1862-1879, Dec. 1985.

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