Modeling of Resistive Type Superconducting Fault Current Limiter

Abstract

In the coming smart grid, among the important issues related to the application of the “Superconducting Fault Current Limiters” (SFCL) is linked to its potential outcome on the decrease of abnormal fault Current. Because of the increased rate of failure currents, SFCL is most likely to enter a media and low-voltage network to reduce the electrical systems' ability and enhance the strength of the devices. All substations providing the distribution of electrical energy are prone to unnecessary voltage or current spikes, affecting facilities such as interruptions in energy supply, resulting in economic loss for the companies that operate them. Currently, no SFCL Simulink model is implemented in the MATLAB database software. A Matlab / Simulink design for the resistive SFCL is suggested in this research paper. This article first presents a resistive style SFCL model using Matlab / Simulink and then replicates distinct fault kinds and analyzes are performed without SFCL and SFCL. The research demonstrates that SFCL reduces the amount of the fault current to a satisfying stage but also reduces the thermal temporary restoration voltage. SFCL also increases the temporary strength, energy performance and efficiency of energy scheme by spontaneously decreasing error flow. The research paper introduces an advanced current limiter implementation based on superconductivity. The theme of the paper revolves around the design of “resistive-type superconducting fault current limiters”.