DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization
-
Published:2022-01-30
Issue:5
Volume:10
Page:24-31
-
ISSN:2277-3878
-
Container-title:International Journal of Recent Technology and Engineering (IJRTE)
-
language:
-
Short-container-title:IJRTE
Author:
Wali Ibtissem, ,Kessentini Amina,Ayed Mohamed Ali Ben,Masmoudi Nouri, , ,
Abstract
The programmable processors newest technologies, as for example the multicore Digital Signal Processors (DSP), offer a promising solution for overcoming the complexity of the real time video encoding application. In this paper, the SHVC video encoder was effectively implemented just on a single core among the eight cores of TMS320C6678 DSP for a Common Intermediate Format (CIF)input video sequence resolution(352x288). Performance optimization of the SHVC encoder had reached up 41% compared to its reference software enabling a real-time implementation of the SHVC encoder for CIF input videos sequence resolution. The proposed SHVC implementation was carried out on different quantization parameters (QP). Several experimental tests had proved our performance achievement for real-time encoding on TMS320C6678.
Publisher
Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
Subject
Management of Technology and Innovation,General Engineering
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Optimal Implementation of the Boxfilter Algorithm Based on Feiteng Platform;2023 IEEE 11th Joint International Information Technology and Artificial Intelligence Conference (ITAIC);2023-12-08