Beamforming Algorithm Architectures for Medical Ultrasound
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Published:2019-10-10
Issue:12
Volume:8
Page:2452-2459
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ISSN:2278-3075
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Container-title:International Journal of Innovative Technology and Exploring Engineering
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language:en
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Short-container-title:IJITEE
Abstract
Medical ultrasound scanners are amongst the most sophisticated signal processing machines in use today. The Beamformer is the brain of whole signal processing system of the scanner [1]. Beamforming allows message transmission or reception to be directed or spatially selective. It is used in receiving beamforming to concentrate the noise signals obtained in the region of concern as reflections from various tissue structures. This paper reviews the various receive beamformer architectures implemented in FPGA/ASIC for ultrasound imaging. Most of the receive beamformers are implemented using the standard technique Delay and Sum. Beamforming in ultrasound instruments for medical imaging has traditionally been implemented using analog delay lines. The concept of dynamic focusing in near field has resulted more complex analog delay structures and were replaced by digital structures. By the availability of high-speed analog to digital converters, and VLSI Technology improvements have now made real time implementation of digital beamformers feasible. The current innovations involve hybrid beamformers utilizing the pros of both analog and digital structures. This paper discusses the evolution of beamforming architectures from analog to digital environment and the current beamformer designs. The changes in beamformer designs in order to be compatible to high frequency probes and yield improved imaging performance, resource optimization, etc. are discussed.
Publisher
Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP
Subject
Electrical and Electronic Engineering,Mechanics of Materials,Civil and Structural Engineering,General Computer Science
Cited by
2 articles.
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1. Design and Development of Parallel Beamformer Model for RTL Verification;Lecture Notes in Networks and Systems;2024
2. FPGA Accelerated QRD-Based Matrix Inversion Core for Signal Processing;Proceedings of the NIELIT's International Conference on Communication, Electronics and Digital Technology;2023