Design & Verification of Serial Peripheral Interface (SPI) Protocol

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Abstract

SPI (Serial Peripheral Interface), which was introduced by the company Motorola, and it is a protocol for communication of serial synchronous about the communication among the master and slave device, which is also used to provide communiqué between microcontroller and many devices which are additional and similar to external Analog to the Digital Converters, Digital to Analog Converters, and EEPROMs. Now a days, communication protocols are at low end. There are two different Protocols: 1) Inter-I2C and 2) SPI. Both of these protocols are well designed for the communications between the Integrated Circuits for communication with On-Board Peripherals. SPI is most commonly used protocol for both intra-chip and inter-chip, and is used at low or medium speed of data-stream transfer. This paper introduces about the quality of SPI Interface Protocol with Single Master and Single Slave configuration, which involves 8-bit of the data transfer and all necessary incorporates features that required for modern applications such as ASIC or SOC (System on Chip). The SPI design is verified and implemented by using System Verilog to show their coverage code and their functional correctness, the entire RTL was written using Verilog for Synthesis and then the Verification architecture is written using System Verilog. The implementation is done using Spartan 3E.

Publisher

Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP

Subject

Management of Technology and Innovation,General Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Low Power SPI Protocol using Clock Gating Techniques;2024 International Conference on Emerging Technologies in Computer Science for Interdisciplinary Applications (ICETCS);2024-04-22

2. Integration of BIST Module for Error Bit Detection in SPI Protocol;Lecture Notes in Electrical Engineering;2024

3. Design and Verification of Five-Stage Pipelined Architecture Using SV-Verification Methodology Module;ICT Systems and Sustainability;2023

4. Design and Implementation of Built-In Self-Test (BIST) Master Slave Communication Using I2C Protocol;Advances in Cognitive Science and Communications;2023

5. Verification of Wishbone Compliant SPI Using System Verilog;Advances in Sustainability Science and Technology;2022-10-02

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