Multi-bit structure improvement methods for multiplier devices of matrix type

Abstract

The article proposes methods for improving the structures of matrix multipliers of multi-digit numbers. Advanced single-bit total adders with paraphrase switched inputs and paraphrase outputs are used, intended as components of high-speed matrix multipliers. Based on the use of such single-bit adders, the structures of matrix multipliers are proposed, characterized by 2 times increased speed, 5 times reduced structural complexity compared to known multipliers based on classical single-bit adders. Optimization of structures of multi-bit matrix multipliers is offered. Comparative estimates of structural and temporal complexities of their circuit implementations depending on the bit size of multiplied binary numbers are given. The use of optimized circuit solutions of matrix multipliers can significantly improve the system characteristics of complex computing devices with many such components in the crystals of microelectronic technologies.