A training method for deep neural network inference accelerators with high tolerance for their hardware imperfection

Abstract

Abstract We propose a novel training method named hardware-conscious software training (HCST) for deep neural network inference accelerators to recover the accuracy degradation due to their hardware imperfections. Existing approaches to the issue, such as the on-chip training and the in situ training, utilize the forward inference data that are obtained by the inference accelerators for the backpropagation. In the approaches, since the memory devices that are used for the weights and the biases are to be switched after each epoch, the total number of the switching in the training process grows too large to avoid the problems of endurance limitation, nonlinearity and asymmetry in the switching of the nonvolatile memories used for the weights and the biases. The proposed training method is totally conducted by software whose forward inference path and backpropagation reflect the hardware imperfections, overcoming all the above problems. The HCST reformulates the mathematical expressions in the forward propagation and the gradient calculation with the backpropagation so that it replicates the hardware structure under the influence of variations in the chip fabrication process. The effectiveness of this approach is validated through the MNIST dataset experiments to manifest its capability to restore the accuracies. A circuit design is also disclosed for measuring the offset voltages and the open loop gains of the operational amplifiers used in the accelerator, showing that the chip area overhead is minor.