A self-bias NAND gate and its application to non-overlapping clock generator for extremely low-voltage CMOS LSIs

Abstract

Abstract This paper presents a self-bias NAND (SBNAND) gate and its application to a non-overlapping (NOL) clock generator for extremely low-voltage CMOS LSIs. The SBNAND, consisting of a main NAND gate and feedback inverter, improves the output performance at extremely low supply voltage V DD by controlling the body-bias voltages V BS of the main NAND gate. Measurements of a proof-of-concept chip demonstrated that our proposed NOL clock generator using SBNANDs can operate at the extremely low V DD of 60 mV.