Device modeling of oxide–semiconductor channel antiferroelectric FETs using half-loop hysteresis for memory operation

Abstract

Abstract In this work, the memory characteristics of oxide–semiconductor (OS) channel antiferroelectric FETs (AFeFETs) are investigated by developing a compact model of AFeFETs. The model consists of an analytic junctionless FeFET model and a newly developed AFe Preisach model. The AFe Preisach model can reproduce arbitrary minor loop measurement results. The key feature of AFeFETs is using the half-loop hysteresis of AFe in contrast to the full hysteresis of Fe. Only a small net charge is required and minority carrier generation is not necessary for erase operation, which is preferable for a typical OS channel. Based on the developed model, we systematically vary the device parameters of the OS channel and AFe gate insulator, analyze the memory window using operation point analysis, and show the potential of OS channel AFeFETs for memory applications.