Author:
Kang Daewoong,Park Hyojin,Kim Dae Hwan,Cho Il Hwan
Abstract
Abstract
In this paper, variation in the parameters of the select transistor of a vertical-NAND (V-NAND) flash memory device is investigated for device optimization and performance evaluation. Device characteristics including threshold voltage (V
TH), subthreshold swing (SS) and off-current (I
OFF) are evaluated using two-dimensional device simulation. An equivalent structure of the V-NAND flash memory select transistor is suggested, which includes a fully depleted silicon-on-insulator MOSFET region and a bulk MOSFET region. The effects on device performance of parameter variation of the select transistor are investigated with physical modeling focusing on two merged MOSFET structures. Vertical channel thickness and channel scaling effects on V
TH, SS and I
OFF are studied. However, the corner shape in the select transistor has a negligible effect on device performance. The simulation results in this work can provide guidance for the design of the select transistor in V-NAND flash memory devices.
Funder
the National Research Foundation of Korea (NRF) grant funded by the Korean government
the National Research Foundation of Korea (NRF) grant funded by the Korea Government
Subject
General Physics and Astronomy,General Engineering