Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors

Abstract

Abstract In this paper, we experimentally examined the threshold voltage (V T) variability and the corner effects in gate-all-around p-type poly-Si junctionless (JL) nanowire (NW) and nanosheet (NS) transistors as a function of various effective channel width. The fabricated devices showed small V T variability characteristics even in poly-Si JL NW channel structure thanks to the improved quality of poly-Si channel by fluorine (F) passivation and reduced channel concentration by boron (B) segregation. In addition, it was found by examining the corner effects that the fabricated devices exhibit accumulation-mode like behaviors. The origins of these phenomena are discussed.