Investigation of Device Performance and Negative Bias Temperature Instability of Plasma Nitrided Oxide in Nanoscale p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor's-Reference-Cited by-同舟云学术

Investigation of Device Performance and Negative Bias Temperature Instability of Plasma Nitrided Oxide in Nanoscale p-Channel Metal–Oxide–Semiconductor Field-Effect Transistor's

Published:2008-04-25 Issue:4 Volume:47 Page:2628-2632
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Han In-Shik,Ji Hee-Hwan,Goo Tae-Gyu,Yoo Ook-Sang,Choi Won-Ho,Na Min-Ki,Kim Yong-Goo,Park Sung-Hyung,Lee Heui-Seung,Kang Young-Seok,Kim Dae-Byung,Lee Hi-Deok

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference7 articles.

1. A thorough investigation of MOSFETs NBTI degradation

2. Suppression of boron penetration for p/sup +/ stacked poly-Si gates by using inductively coupled N2 plasma treatment

3. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

4. Interface trap and oxide charge generation under negative bias temperature instability of p-channel metal-oxide-semiconductor field-effect transistors with ultrathin plasma-nitrided SiON gate dielectrics

5. Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Negative Bias Temperature Instability for Sputtering Modification in a TiN Diffusion Barrier of p+ Polysilicon Gate Stack in 50-nm DRAM Technology;IEEE Transactions on Device and Materials Reliability;2013-03

2. Defect Generation and Severity Comparison of Negative Bias Temperature Stress-Induced Degradation on 90 nm p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Different Oxide Thicknesses;Japanese Journal of Applied Physics;2010-04-20