A0.4 µmGate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories-Reference-Cited by-同舟云学术

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A0.4 µmGate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories

Published:1995-02-28 Issue:Part 1, No. 2B Volume:34 Page:895-899
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Maegawa Shigeto,Ipposhi Takashi,Maeda Shigenobu,Nishimura Hisayuki,Tanina Osamu,Kuriyama Hirotada,Inoue Yasuo,Nishimura Tadashi,Tsubouchi Natsuro

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Modeling of Surrounding Gate MOSFETs With Bulk Trap States;IEEE Transactions on Electron Devices;2007-01

2. A Self-Aligned Gate-All-Around MOS Transistor on Single-Grain Silicon;Electrochemical and Solid-State Letters;2004

3. Sram Chips;Wiley Encyclopedia of Electrical and Electronics Engineering;1999-12-27

4. An asymmetric memory cell using a C-TFT for single-bit-line SRAM's;IEEE Transactions on Electron Devices;1999-05

5. Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's;IEEE Transactions on Electron Devices;1999

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