Analysis and Comparison of Polysilicon Contacted Ultra-Shallow Junction p +- and n +-poly Gate p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors by Two-Dimensional Simulation

Abstract

An alternative process for ultra-shallow junction p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) is proposed in this paper. The doping of the source/drain is accomplished by diffusion from a heavily doped overlayer of polycrystalline silicon. Both p +- and n +-poly gate devices with this diffusion technology are compared and evaluated for a channel length of 0.12 µm. We model transistors obtained by industrial integrated circuit technology on the basis of data provided by the chip manufacture. Results of simulation reveal that extremely shallow 0.05 µm junctions can be achieved, and laterally uniform delineated junctions are observed. As in the traditional process, the problems of punchthrough current and drain induced barrier lowering are effectively suppressed by the proposed p +-poly gate device. The superior subthreshold behavior makes the device suitable for applications in low-voltage and low-power circuit.