Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
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1. A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor;IPSJ Transactions on System and LSI Design Methodology;2023
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