Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-$k$/Cu Back End on the Line Layers-Reference-Cited by-同舟云学术

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Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-$k$/Cu Back End on the Line Layers

Published:2012-02-20 Issue:2 Volume:51 Page:02BB01
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Kume Ippei,Inoue Naoya,Hijioka Ken'ichiro,Kawahara Jun,Takeda Kouichi,Furutake Naoya,Shirai Hiroki,Kazama Kenya,Kuwabara Shin'ichi,Watarai Msasatoshi,Sakoh Takashi,Takahashi Takafumi,Ogura Takashi,Taiji Toshiji,Kasama Yoshiko,Sakamoto Misato,Hane Masami,Hayashi Yoshihiro

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference9 articles.

1. An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

2. Relation between critical current of domain wall motion and wire dimension in perpendicularly magnetized Co/Ni nanowires

3. Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

4. Low write-current magnetic random access memory cell with anisotropy-varied free layers

5. Resistance Controllability of $\hbox{Ta}_{2} \hbox{O}_{5}/\hbox{TiO}_{2}$ Stack ReRAM for Low-Voltage and Multilevel Operation

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