Extreme Ultraviolet Process Optimization for Contact Layer of 14 nm Node Logic and 16 nm Half Pitch Memory Devices-Reference-Cited by-同舟云学术

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Extreme Ultraviolet Process Optimization for Contact Layer of 14 nm Node Logic and 16 nm Half Pitch Memory Devices

Published:2012-06-20 Issue: Volume:51 Page:06FB03
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Tseng Shih-En,Chen Alek

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Direct-Write NiO RRAM Cells;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Fabrication of 120-nm-channel-length ferroelectric-gate thin-film transistor by nanoimprint lithography;Japanese Journal of Applied Physics;2014-01-29

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