Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,General Engineering
Link
http://stacks.iop.org/1882-0786/3/i=2/a=025002/pdf
Reference12 articles.
1. A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology
2. A single electron binary-decision-diagram quantum logic circuit based on Schottky wrap gate control of a GaAs nanowire hexagon
3. Fabrication of GaAs-based integrated half and full adders by novel hexagonal BDD quantum circuit approach
4. Schottky Wrap Gate Control of Semiconductor Nanowire Networks for Novel Quantum Nanodevice-Integrated Logic Circuits Utilizing BDD Architecture
5. A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology
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1. Self-assembled semiconductor quantum dots decorating the facets of GaAs nanowire for single-photon emission;National Science Review;2017-03-01
2. Implementation of a noise-coexistence threshold logic architecture on a GaAs-based nanowire FET network;International Journal of Parallel, Emergent and Distributed Systems;2016-07
3. Synthesis for Width Minimization in the Single-Electron Transistor Array;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-12
4. Boolean Logic Circuits on Nanowire Networks and Related Technologies;Nanophotonic Information Physics;2013-12-08
5. Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET);Microelectronics Journal;2013-12
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