1. [1] S. -M. Kim, S. -Y. Koo, J. -S. Choi, Y. -S. Hwang, J. -W. Park, E. -K. Kang, C. -M. Lim, S. -C. Moon, J. -W. Kim, "Issue and Challenges of Double Patterning Lithography in DRAM", Proc. of SPIE, 6520, 65200H-1 (2007)
2. [2] M. O. Beeck, J. Versluijs, V. Wiaux, T. Vandeweyer, I. Ciofi, H. Struyf, D. Hendrckx, J. V. Olmen, "Manufacturability Issues with Double Patterning for 50nm Half Pitch Single Damascene Applications, Using RELACS Shrink and Corresponding OPC" , Proc. of SPIE, 6520, 65200I-1 (2007)
3. [3] W. -Y. Jung, S. -M. Kim, C. -D. Kim, G. -H. Sim, S. -M. Jeon, S. -W. Park, B. -S. Lee, S. -K. Park, J. -S. Kim, L. -S. Heon, "Patterning with Amorphous Carbon Spacer for Expanding the Resolution Limit of Current Lithography Tool" , Proc. of SPIE, 6520, 65201C-1 (2007)
4. [4] H. Nakamura, M. Omura, S. Yamashita, Y. Taniguchi, J. Abe, S. Tanaka, S. Inoue, "Ultra-low k1 Oxide Contact Hole Formation and Metal Filling Using Resist Contact Hole Pattern by Double L&S Formation Method" , Proc. of SPIE, 6520, 65201E-1 (2007)
5. [5] H. J. Liu, W. H. Hsieh, C. H. Yeh, J. S. Wu, H. W. Chan, W. B. Wu, F. Y. Chen, T. Y. Huang, C. L. Shin, J. P. Lin, "Double Patterning with Multilayer Hard Mask Shrinkage for sub-0.25k1 Lithography" , Proc. of SPIE, 6520, 65202J-1 (2007)