(Invited) Wafer Scale Copper Direct Plating on Thin PVD RuTa Layers: A Route to Enable Filling 30 nm Features and Below

Abstract

Among all the Ru-based substrates, mixed-phase RuTa liners grown by physical vapor deposition have been explored as potential directly-platable diffusion barrier candidates. In order to understand the full-wafer copper direct plating process that occurs on these liners, the effect of the applied waveform, electrical contacts and suppressor chemistry have been investigated. In order to enhance copper nucleation and wafer scale edge-to-center copper front propagation rate, a liner surface cleaning protocol is developed. The copper front propagation across the 300 mm wafer is reported as a function of the RuTa film thickness. An optimized copper direct plating process on RuTa layers as thin as 4 nm is integrated in 90 and 30 nm half pitch single and dual damascene structures. Results in terms of compatibility of the direct plated copper with the following chemical mechanical planarization step complemented with physical and electrical characterization data are reported. The direct filling of ~25 nm sacrificial fin structures is also investigated.